1. Field of the Invention
The present invention relates to a processor, and more particularly, to a method for processing data in a processor which is capable of efficiently executing a program including a repeat block (referred to as RPTB, hereinafter).
2. Description of the Background Art
FIG. 1 is a block diagram of a processor for performing a program including the RPTB command in accordance with conventional art.
As shown in the drawing, a processor core 100 includes an operation logic and a partial control logic and processes a command stored in a program memory 101 in a pipeline form, that is, in three steps of fetch (F)—decode (D)—read/execute (R/E). The memory 101, a general term in use for a processor, stores a command to be decoded by the processor core 100. A program counter generation logic 106 generates a program counter (PC) value under the control of the processor core 100, and the generated PC value is stored in a program counter 108 through a multiplexer 107. The PC value is the memory address to be fetched during an operational cycle of a processor.
A RPTB control logic 102, a repeat count (RC) register 103, a repeat ending register 104, and a repeat starting register 105 for the repeat block (RPTB) logic. The RPTB control logic 102 is operated by an enable signal outputted from the processor core 100, and when it carries out a RPTB command, it controls the repeat counter (RC) register 103, the repeat ending (RE) register 104, the repeat starting (RS) register 105 and the multiplexer (MUX) 107.
The repeat counter (RC) register 103 stores a repeat count value (repeating number) (BRC), and the repeat ending (RE) register 104 and the repeat starting (RS) register 105 store a repeat ending address (REA) and a repeat starting address (RSA), respectively.
The RPTB control logic 102 compares a memory address stored in the program counter 108 with the repeat ending address (REA), and if the two addresses are the same, the RPTB control logic 102 controls the multiplexer 107 so that the repeat starting address (RS) stored in the RS register 105 is inputted to the program counter 108 and a reduction signal is outputted to the RC register 103 to reduce the repeat count value (BRC).
The operation of the processor in accordance with the conventional art, as described above, will now be explained in the process of executing <Program 1> below.
The repeat count value (BRC) is set to ‘1’ and the repeat ending address (REA) of the RPTB command is set to ‘n+3’. The repeat block includes three commands “CALL”, “ADD” and “SUB”.
<Program 1>STMBRC#2n − 1RPTBn + 3 nCALLn + 10n + 1ADDn + 2SUBn + 3RET n + 10NOP n + 11NOP
FIG. 3 is an exemplary view showing how each command of <Program 1> is processed in the pipeline.
In the first cycle 60, the processor core 100 fetches a command “STM” corresponding to a memory address (n−1) outputted from the program counter 108 from the memory 101.
In the second cycle 61, the processor core 100 decodes the fetched command “STM” and outputs a control signal for storing the repeat count value (BRC) ‘2’ to the RPTB control logic 102. The processor core 100 controls the PC generation logic 106 so that the present PC value (n) is increased to be the next PC value (n+1), and fetches the command “RPTB” corresponding to memory address (n) of the program counter 108 from the memory 101.
In the third cycle 62, the RPTB control logic 102 sets repeat count values (BRC) of ‘2’ in the RC register 103. The processor core 100 decodes the fetched “RPTB” command to output an enable signal and a repeat ending address (REA) to the RPTB control logic 102, and controls the PC generation logic 106 so that the current value is increased to be the next PC value (n+2). Also, the processor core 100 fetches a command “CALL” corresponding to the memory address (n+1) of the program counter 108 from the memory 101.
In the fourth cycle 63, the RPTB control logic 102 is enabled by the execution of the “RPTB” command to set the repeat ending address (REA) of (n+3) in the RE register 104 and to set the memory address (n+2) outputted from the program counter 108 as a repeat starting address (RSA) in the RS register 105. That is, the RPTB control logic 102 sets the address (n+3) of the executed RPTB command as the repeat ending address (REA) and the memory address (n+2) of the program counter 108 as a repeat starting address (RSA).
After the processor core 100 decodes the command “CALL”, the processor core controls the memory 101 so as to store the memory address (n+2) outputted from the program counter 108, and controls the PC generation logic 106 so as to generate the next PC value (n+10). At this time, since the repeat ending address (REA) (n+3) is different from the memory address (n+2) of the program counter 108, the RPTB control logic 102 does not perform any controlling operation. The processor core 100 also fetches the command “ADD” corresponding to the memory address (n+2).
In the fifth cycle 64, the memory 101 stores the memory address (n+2). The processor core 100 does not decode the fetched command “ADD” since the previous command was “CALL”, and controls the PC generation logic 106 so that the present PC value will be increased to be (n+11). And, the processor core 100 fetches a command “RET” corresponding to the memory address (n+10).
In the sixth cycle 65, since the command “ADD” was not decoded, the processor core 100 does not execute the command “ADD”. The processor core 100 decodes the fetched command “RET”. Since the command “RET” signifies a return, the processor core 100 reads out the memory address (n+2) previously stored in the memory 101 and controls the PC generation logic 106 so that the memory address (n+2) will be set again as a PC value. And, the processor core 100 fetches a command “NOP” corresponding to memory address (n+11).
In the seventh cycle 66, since returning operation is being performed, the processor core 100 executes nothing. The processor core 100 decodes the fetched command “NOP”, and controls the PC generation logic 106 so that the present PC value (n+2) will be increased to (n+3). And, the processor core 100 fetches the command “ADD” corresponding to memory address (n+2) from the memory 101.
In the eighth cycle 67, since the command “NOP” is ‘No operation’, the processor core 100 executes nothing. And, the processor core 100 decodes the fetched command “ADD” and controls the PC generation logic so as to generate the next PC value (n+4). Since the present PC value (n+3) is identical to the repeat ending address (REA)(n+3) of the RE register 104, the RPTB control logic 102 controls the RS register 105 and the multiplexer 107 so that the repeat starting address (RSA) of (n+1) is inputted to the program counter 108. And, the RPTB control logic 102 outputs a reduction signal to the RC register 103. And the processor core 100 fetches a command “SUB” corresponding to the memory address (n+3) from the memory 101.
In the ninth cycle 68, the processor core 100 executes the command “ADD”, and the RC register 103 reduces the repeat count value (BRC) from ‘2’ to ‘1’ in accordance to the reduction signal. And, the processor core 100 decodes the command “SUB” and fetches the command “CALL” from the memory address (n+1).
Thereafter, the operations from the fourth cycle 63 to the eighth cycle 67 are repeated, and when the PC value (n+3) is identical to the repeat ending address (REA) again, the RPTB control logic 102 outputs a reduction signal to the RC register 103. Then, the RC register 103 reduces the repeat count value (BRC) to ‘0’ according to the reduction signal, and when the repeat count value (BRC) of the RC register 103 becomes ‘0’, the processor core 100 disables the RPTB control logic 102.
In addition, the data process operation of the conventional process will described in executing <Program 2> below.
<Program 2>STMBRC#2n − 1RPTBn + 2 nCALLn + 10n + 1ADDn + 2RET n + 10NOP n + 11
In <Program 2>, the repeat count value (BRC) is set as ‘2’, the same as that of <Program 1>. Meanwhile, unlike <Program 1>, the repeat ending address (REA) is set by ‘n+2’ in <Program 2>, and the repeat block includes only the commands of “CALL” and “ADD”. Thus, in the case of executing <Program 2>, the first cycle 70 through the third cycle 72 are the same as those of <Program 1>.
In the fourth cycle 73, the RPTB control logic 102 sets the repeat ending address (REA) as (n+2) and the repeat starting address (RSA) as (n+1). After decoding the fetched command “CALL”, the processor core 100 controls the PC generation logic 106 so that the memory address (n+2) can be stored in the memory 101. Also, the processor core 100 controls the PC generation logic 106 so that (n+10) becomes the next PC value. At this time, since the present PC value (n+2) is identical to the repeat ending address (REA), the RPTB control logic 102 outputs a reduction signal to the RC register 103. And, the processor core 100 fetches the command “ADD” corresponding to the memory address (n+2).
Thereafter, in the fifth cycle 74, the memory 101 stores the memory address (n+2), and the RC register 103 reduces the repeat count value (BRC) from ‘2’ to ‘1’ according to the reduction signal. Since the previous command is “CALL”, the processor core 100 does not decode the fetched command “ADD”, and controls the PC generation logic 106 so that the present PC value (n+10) will be increased to (n+11). And, the processor core 100 fetches the command “RET” corresponding to the memory address (n+10).
In the sixth cycle 65, since the command “ADD” was not decoded, the processor core 100 does not execute the command “ADD”. The processor core 100 decodes the fetched command “RET”. Since the command “RET” signifies a return, the processor core 100 reads out the memory address (n+2) previously stored in the memory 101 and controls the PC generation logic 106 so that the memory address (n+2) will be set again as a PC value. And, the processor core 100 fetches a command “NOP” corresponding to memory address (n+11).
In the seventh cycle 76, since the returning operation is being performed, the processor core 100 executes nothing. The processor 100 decodes the fetched command “NOP” and fetches the command “ADD” corresponding to the memory address (n+2).
At this time, since the memory address (n+2) stored in the memory 101 is identical to the repeat ending address (REA), the RPTB control logic 102 outputs again the reduction signal to the RC register 103 and controls the RS register 105 and the multiplexer 107 so that the repeat starting address (RSA) of (n+1) will be the program counter value.
Accordingly, in the eighth cycle 77, the repeat count value (BRC) of the RC register 103 is reduced from ‘1’ to ‘0’, and at this time, the processor core 100 disables the RPTB control logic 102.
Here, it is noted that <Program 2> is executed differently from what was intended. That is, in <Program 2>, after “CALL”, that is, the command of memory address (n+1) is decoded, the repeat count value (BRC) is reduced once but the “ADD” is not decoded or executed. Then after “CALL” is finished and the “RET” is executed, the repeat count value (BRC) is reduced again and the “ADD” is only executed once.
As a result of the “CALL”, the “ADD” was actually executed once by the RPTB. The “ADD” was not executed as twice as designated by the repeat count register 103. Thus, the conventional processor has a problem in that at least three commands should be included in the RPTB to guarantee a reliability of the program.
Originally, the processor receives an unexpected input from external source as an interrupt, and upon receipt of it, the processor stores the current state (including an address), performs a specific program and returns to the previous state. This is quite similar to the “CALL” command. In a program including a repeat block consisting of more than three commands, if an interrupt comes in while the processor is executing the final portion (after a control signal is outputted to reduce the BRC) of the repeat block, the processor executes the interrupt and does not return to the previous state. The reason for this is that an execution was lost as a result of the interrupt. Accordingly, in the general processor of the conventional art, when the processor is interrupted while it is executing the final part of the repeat block, the program is not properly executed due to an inaccurate reduction of the repeat count value (BRC).
A possible solution to the problem would be that an interrupt is not to be applied while the final command of a repeat block is being executed. But forcibly blocking the interrupt to a command, which should be subordinate to the interrupt, would degrade efficiency of an application program.